The operation times for the major functional units are 200ps for memory access, 200ps for ALU operation, and 100ps for register file read or write. For example, in single-cycle design, the time required for every instruction is 800ps due to lw instruction (instruction fetch, register read, ALU operation, data access, and register write). Here, we only consider lw instruction for speedup comparison. [2 pts]


a. If the time for an ALU operation can be shortened by 25%, will it affect the speedup obtained from pipelining? If yes, why? Otherwise, why?

b. What if the ALU operation now takes 25% more time? Will it affect the speedup obtained from pipelining? If yes, why? Otherwise, why? Then what is clock cycle time?