The MIPS processor described in this course uses 32-bit CPU registers. Integers that are 64 bits in size can be handled on the MIPS processor by using a pair of 32-bit registers. An even numbered register is used to hold the leftmost 32 bits of the 64-bit integer and the next higher odd numbered register is used to hold the rightmost 32 bits of the 64-bit integer. Assume that MIPS register $2 contains the decimal value 169482938 and register $3 contains the decimal value 1516927626. Register $4 contains the decimal value 455818059 and $5 contains the decimal value 1264282507. The IA-32 processors with multi-media extensions include 64-bit MMX registers that can hold 64-bit integers. Assume that the 64-bit IA-32 MM2 register contains the same 64-bit pattern as the 64-bit integer in MIPS registers $2 and $3. Also assume that 64-bit IA-32 register MM4 contains the same 64-bit pattern as the 64-bit integer in MIPS registers $4 and $5. a) (3) Show, in hex, the contents of register MM2 after the IA-32 instruction PADDB MM2, MM4 is executed. contents of MM2 = 0x___________ b) (3) Show, in hex, the contents of MIPS registers $2 and $3 after the following two MIPS instructions are executed: addu $2, $2, $4 addu $3, $3, $5 $2 in hex = 0x______ $3 in hex = 0x________________.